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What Is a Control Bus?

By C. K. Lanz
Updated May 16, 2024
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A control bus is what a computer’s central processing unit (CPU) uses to communicate with other devices inside the machine over a set of physical connections like cables or printed circuits. It is a diverse collection of signals, including read, write, and interrupt, that allow the CPU to direct and monitor what the different parts of the computer are doing. This is one of three types of buses that make up the system or computer bus. Its exact composition varies among processors.

In general, the purpose of any bus is to decrease the number of pathways necessary for communication between computer components. A bus allows communication between components over one data channel and is characterized by how much information it can transmit at once. The amount of data is expressed in bits and corresponds to the number of physical lines over which the information is sent. For example, a ribbon cable with 32 wires can send 32 bits in parallel.

Each computer usually has an internal and an expansion bus. The internal or front-side bus facilitates communication between the CPU and the central memory, while the expansion or input/output bus links the motherboard components like hard drives and ports. Most system buses are typically composed of between 50 and 100 separate physical lines for communication. These lines are subdivided into three subassemblies or types of buses: the address or memory bus, the data bus, and the command or control bus.

The control bus is bidirectional; it transmits command signals from the CPU and response signals from the hardware. It helps the CPU synchronize its command signals to the computer’s components and slower external devices. As a result, the control bus consists of control lines that each send a specific signal, like read, write, and interrupt. The control lines that make up a control bus differ between processors, but most include system clock lines, status lines, and byte enable lines.

For example, a computer’s CPU will use the data bus to transmit information to and from the central memory. The control bus allows the CPU to determine whether and when the system is sending or receiving this data. This is because a control bus has a control line for read and one for write that determine the direction the information flows (memory to CPU or CPU to memory). If the CPU needs to write some data to the central memory, it will send a signal on (assert) the control bus’s write control line. Sending a signal on the read control line allows the CPU to receive data from memory.

The other types of buses that make up a system bus are the data and address buses. The data bus moves instructions and information between all the functional computer components. It is bidirectional and can transmit in only one direction at a time. The data bus transmits information between the CPU and memory and also between memory and the input/output section.

The address bus is unidirectional and functions like a map for the memory. When the computer system needs to access a particular memory location or input/output device, it asserts the appropriate address on the address bus. This address is recognized by the appropriate circuitry that then instructs the corresponding memory or device to read or send data on the data bus. Only the device or memory location that corresponds to the address on the address bus will respond.

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Discussion Comments

By Logicfest — On Feb 14, 2014

And the more complex CPUs get, the more complex (and larger) these devices can become. One things worth pointing out is that the number of "bits" a CPU has doesn't mean much if the bus doesn't take advantage of it.

For example, the old IBM PCs had an Intel 8088 CPU. The bus, however, was only 8 bits wide, meaning the CPU could only send and receive data in an 8 bit data path. Similarly, some 32-bit CPUs were nestled in 16-bit buses, thus depriving users of the expected performance gain.

A bus doesn't get the attention as the "geek numbers" of snazzy CPUs and that can be misleading to consumers.

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