An address bus is a computer bus which is used to address the main system memory. In many embedded controllers and some older computers, the processor address bus is directly wired to the memory chips. Most desktop and server motherboards include the address bus in the memory bus between the memory controller chip and the system memory. The address bus is used by a processor to indicate the memory location that it is about to read data from or write data to. Some processors may also use it to indicate an input/output port that is about to be read or written.
Some computers have direct connections from the address bus of the processor and other system devices to the main memory. Many peripheral controllers can share system memory with the processor using a technique called Direct Memory Access (DMA). A network, hard disk or graphics controller may be a DMA-enabled device. This allows the controller to transfer data to and from the system faster than sending it through the processor one piece at a time.
Regardless of whether the physical address comes from the processor or a DMA device, it is latched onto the address bus. This action alerts the memory that a read or write request for that memory address is about to be made. If a write operation is pending, the data to be written is latched onto the data bus and a memory write signal is triggered. A read operation can be performed by triggering the memory read signal and reading the data bus.
Most personal computer (PC) compatible servers and desktops use a memory controller chip which is separate from the main processor. This controller communicates with the main system memory over the memory bus. This bus includes the address bus, data bus and many control signals. The memory controller is located in the northbridge device and interfaces with the main processor using the front-side bus (FSB).
The northbridge memory controller and the FSB can create a bottleneck in some systems, slowing the processor's memory access. For this reason, a system's high-speed cache memory uses an entirely separate and wider cache bus. The cache is directly connected to the processor through this bus, bypassing the FSB and the northbridge completely. The cache bus, also known as the back-side bus (BSB), functions as an address bus, data bus and control bus for the cache memory exclusively.
Some PC-compatible processors include a memory controller in the main processor itself. This controller accesses the main system memory directly, without using the FSB or the northbridge device. With these bottlenecks removed, the processor spends less time waiting on main system memory accesses. Cache memory is often included in these processors as well, and any external cache is accessed through the cache bus.